Managing batch processors to reduce lead time in a semiconductor packaging line

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Please use this identifier to cite or link to this item: http://hdl.handle.net/11718/9474

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DC Field	Value	Language
dc.contributor.author	Chandra, Pankaj
dc.contributor.author	Gupta, S.
dc.date.accessioned	2010-10-08T11:34:42Z
dc.date.available	2010-10-08T11:34:42Z
dc.date.copyright	1997
dc.date.issued	1997-10-08T11:34:42Z
dc.identifier.uri	http://hdl.handle.net/11718/9474
dc.description	International Journal of Production Research, Vol. 35, No. 3, (1997), pp. 611-633	en
dc.description.abstract	In this paper we study a semiconductor packaging line at IBM Bromont. At the line, modules are assembled and then tested in a burn-in oven. The burn-in oven is a batch processing station. We outline a procedure to determine order release schedule and lot sizes for the various work stations in the line, such that total manufacturing lead time is minimized. The internal parameters of the procedure are set by simulation experiments and by heuristics. Sensitivity analysis is carried out to determine the robustness of the procedure with respect to various external parameter settings.
dc.language.iso	en	en
dc.subject	Semiconductor	en
dc.subject	Lead Time	en
dc.title	Managing batch processors to reduce lead time in a semiconductor packaging line	en
dc.type	Article	en
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